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ds07-16702-3e fujitsu semiconductor data sheet copyright?2005-2007 fujitsu limited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 32 - bit proprietary microcontrollers cmos fr60lite mb91265a series mb91266a/mb91f267a/MB91F267NA/mb91v265a description the mb91265a series is a 32-bit risc microcontroller designed by fujitsu for embedded control applications which require high-speed processing. the cpu is used the fr family* and the compatibility of fr60lite. MB91F267NA loads the c-can (1 channel) . * : fr, the abbreviation of fujitsu risc contro ller, is a line of products of fujitsu limited. features ? fr60lite cpu 32-bit risc, load/store architecture with a five-stage pipeline maximum operating frequency : 33 mhz (oscillation fr equency 4.192 mhz, oscillation frequency 8-multiplier (pll clock multiplication method) 16-bit fixed length instructions (basic instructions) execution speed of instructions : 1 instruction per cycle memory-to-memory transfer, bit handling, barrel shift inst ructions, etc. : instructions suitable for embedded applications function entry/exit instructions, multiple-register lo ad/store instructions : inst ructions adapted for c-language register interlock function : facilitates coding in assembler. built-in multiplier with instruction-level support ? 32-bit multiplication with sign : 5 cycles ? 16-bit multiplication with sign : 3 cycles interrupt (pc, ps save) : 6 cycles, 16 priority levels harvard architecture allowing program access and data access to be executed simultaneously instruction compatible with fr family (continued)
mb91265a series 2 (continued) ? internal peripheral functions capacity of internal rom and rom type mask rom : 64 kbytes (mb91266a) flash rom : 128 kbytes (mb91f267a/MB91F267NA) : 24 kbytes (evaluation model*) * : evaluation model is mb91v265a. capacity of internal ram : 2 kbytes (mask product)/4 kbytes (flash memory product) a/d converter (sequential comparison type) resolution : 8/10 bits : 4 channels 1 unit, 7 channels 1 unit conversion time : 1.2 s (minimum conversion time system clock at 33 mhz) 1.35 s (minimum conversion time system clock at 20 mhz) external interrupt input : 8 channels bit search module (for realos) function for searching the msb (upper bit) in each word for the first 1-to-0 inverted bit position c-can 32msb : 1 channel (l oaded in MB91F267NA only) uart (full-duplex double buffer) : 2 channels selectable parity on/off asynchronous (start-stop synchronized) or clock-synchronous communications selectable internal timer for dedicated ba ud rate (u-timer) on each channel external clock can be used as transfer clock error detection function for parity, frame, and overrun errors 8/16-bit ppg timer : 8 channels (a t 8-bit) / 4 channels (at 16-bit) timing generator 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0) 16-bit free-run timer : 3 channels 16-bit pwc timer : 1 channel input capture : 4 channels (interface with free-run timer) output compare : 6 channels (interface with free-run timer) waveform generator various waveforms which are generated by using output compare, 16-bit ppg timer 0, and 16-bit dead timer sum of products macro ram : instruction ram (i-ram) 256 16-bit coefficient ram (x-ram) 64 16-bit variable ram (y-ram) 64 16-bit execution of 1 cycle mac (16-bit 16-bit + 40 bits) operation results are extracted rounded from 40 to 16 bits dmac (dma controller) : 5 channels operation of transfer and activation by internal peripheral interrupts and software watchdog timer low-power consumption mode sleep/stop function package : lqfp-64p technology : cmos 0.35 m power supply : 1-power supply (vcc = 4.0 v to 5.5 v)
mb91265a series 3 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 av ss acc an0/p50 an1/p51 an2/p52 an3/p53 an4/p54 an5/p55 an6/p56 an7/p57 an8/p44 an9/p45 an10/p46 nmi c v ss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss x1 x0 md0 md1 md2 pg1/ppg0 p27 p26/ic1 p25/ic0 p24/cki p23/dtti p22/pwi0 p21/adtg2/ic3 p20/adtg1/ic2 p17/ppg6/tx0* 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 av cc avrh2 avrh1 p43/int3 p42/int2 p41/int1 p40/int0 p30/rto0 p31/rto1 p32/rto2 p33/rto3 p34/rto4 p35/rto5 init p36/ppg7/int7 p37/ppg4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v cc p00/ppg1/int4 p01/ppg2 p02/ppg3/int5 p03/tin0 p04/tin1 p05/tin2 p06/tot1 p07/tot2 p10/sot0 p11/sin0 p12/sck0 p13/sot1 p14/sin1 p15/sck1 p16/ppg5/int6/rx0* (fpt-64p-m23) (top view) * : c-can pin is loaded in only MB91F267NA.
mb91265a series 4 pin description (continued) pin no. pin name i/o circuit type* 1 description 3 an0 g analog input terminal of a/d converter 1. this function becomes valid when set the corresponding aicr1 register to analog input. p50 general purpose input/output port. this function becomes valid when analog input is set to disabled. 4 an1 g analog input terminal of a/d converter 1. this function becomes valid when set the corresponding aicr1 register to analog input. p51 general purpose input/output port. this function becomes valid when analog input is set to disabled. 5 an2 g analog input terminal of a/d converter 1. this function becomes valid when set the corresponding aicr1 register to analog input. p52 general purpose input/output port. this function becomes valid when analog input is set to disabled. 6 an3 g analog input terminal of a/d converter 1. this function becomes valid when set the corresponding aicr1 register to analog input. p53 general purpose input/output port. this function becomes valid when analog input is set to disabled. 7 an4 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p54 general purpose input/output port. this function becomes valid when analog input is set to disabled. 8 an5 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p55 general purpose input/output port. this function becomes valid when analog input is set to disabled. 9 an6 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p56 general purpose input/output port. this function becomes valid when analog input is set to disabled. 10 an7 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p57 general purpose input/output port. this function becomes valid when analog input is set to disabled. 11 an8 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p44 general purpose input/output port. this function becomes valid when analog input is set to disabled. 12 an9 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p45 general purpose input/output port. this function becomes valid when analog input is set to disabled.
mb91265a series 5 (continued) pin no. pin name i/o circuit type* 1 description 13 an10 g analog input terminal of a/d converter 2. this function becomes valid when set the corresponding aicr2 register to analog input. p46 general purpose input/output port. this function becomes valid when analog input is set to disabled. 14 nmi h nmi (non maskable interrupt) input terminal. 18 int4 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. ppg1 output terminal of ppg timer 1. this function becomes valid when output of ppg timer 1 is set to enabled. p00 general purpose input/output port. this function becomes valid when output of ppg timer 1 and external interrupt input are set to disabled. 19 ppg2 d output terminal of ppg timer 2. this function becomes valid when output of ppg timer 2 is set to enabled. p01 general purpose input/output port. this function becomes valid when output of ppg timer 2 is set to disabled. 20 int5 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. ppg3 output terminal of ppg timer 3. this function becomes valid when output of ppg timer 3 is set to enabled. p02 general purpose input/output port. this function becomes valid when output of ppg timer 3 and external interrupt input are set to disabled. 21 tin0 d external trigger input terminal of reload timer 0. since this input is used as required while t he trigger input is e nabled, the port output must remain off unless intentionally used. p03 general purpose input/output port. this function becomes valid when external clock input of reload timer 0 is set to disabled. 22 tin1 d external trigger input terminal of reload timer 1. since this input is used as required while t he trigger input is e nabled, the port output must remain off unless intentionally used. p04 general purpose input/output port. this function becomes valid when external clock input of reload timer 1 is set to disabled. 23 tin2 d external trigger input terminal of reload timer 2. since this input is used as required while t he trigger input is e nabled, the port output must remain off unless intentionally used. p05 general purpose input/output port. this function becomes valid when external clock input of reload timer 2 is set to disabled.
mb91265a series 6 (continued) pin no. pin name i/o circuit type* 1 description 24 tot1 d output terminal of reload timer 1. this function becomes valid when output of reload timer 1 is set to enabled. p06 general purpose input/output port. this function becomes valid when output of reload timer 1 is set to disabled. 25 tot2 d output terminal of reload timer 2. this function becomes valid when output of reload timer 2 is set to enabled. p07 general purpose input/output port. this function becomes valid when output of reload timer 2 is set to disabled. 26 sot0 d uart0 data output terminal. this function becomes valid when data output of uart0 is set to enabled. p10 general purpose input/output port. this function becomes valid when data output of uart0 is set to disabled. 27 sin0 d uart0 data input terminal. since this input is used as required while t he uart0 input is enabled, the port output must remain off unless intentionally used. p11 general purpose input/output port. this function becomes valid when data input of uart0 is set to disabled. 28 sck0 d uart0 clock input/output terminal. this function becomes valid when clock output of uart0 is set to enabled. p12 general purpose input/output port. this function becomes valid when clock ou tput of uart0 is set to disabled. 29 sot1 d uart1 data output terminal. this function becomes valid when data output of uart1 is set to enabled. p13 general purpose input/output port. this function becomes valid when data output of uart1 is set to disabled. 30 sin1 d uart1 data input terminal. since this input is used as required while t he uart1 input is enabled, the port output must remain off unless intentionally used. p14 general purpose input/output port. this function becomes valid when data input of uart1 is set to disabled. 31 sck1 d uart1 clock input/output terminal. this function becomes valid when clock output of uart1 is set to enabled. p15 general purpose input/output port. this function becomes valid when clock ou tput of uart1 is set to disabled.
mb91265a series 7 (continued) pin no. pin name i/o circuit type* 1 description 32 int6 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. ppg5 output terminal of ppg timer 5. this function becomes valid when output of ppg timer 5 is set to enabled. rx0 rx0 input terminal of c-can0 (MB91F267NA only ) . since this input is used as required while the rx0 input is enabl ed, port output must remain off unless intentionally used. p16 general purpose input/output port. this function becomes valid when output of ppg timer 5 and rx0 input* 2 of c-can0 are set to disabled. 33 ppg6 d output terminal of ppg timer 6. this function becomes valid when output of ppg timer 6 is set to enabled. tx0 tx0 output terminal of c-can0 (only MB91F267NA) . this function becomes valid when tx0 output of c-can0 is set to enabled. p17 general purpose input/output port. this function becomes valid when out put of ppg timer 6 and tx0 output* 2 of c-can0 are set to disabled. 34 adtg1 d external trigger input terminal of a/d converter 1. since this input is used as required while it selects as a/d activation trigger cause, the port output must remain off unless intentionally used. ic2 trigger input terminal of input capture 2. the port can serve as an input when set for input with the setting of the input capture trigger input. when the port is used for input capture inpu t, this input is used as required. the port output must theref ore remain off unless intentionally used. p20 general purpose input/output port. this function becomes valid when the settin g of the external trigger input of a/d converter 1 or the setting of the input capture trigger input is set to disabled. 35 adtg2 d external trigger input terminal of a/d converter 2. since this input is used as required while it selects as a/d activation trigger cause, the port output must remain off unless intentionally used. ic3 trigger input terminal of input capture 3. the port can serve as an input when set for input with the setting of the input capture trigger input. when the port is used for input capture inpu t, this input is used as required. the port output must theref ore remain off unless intentionally used. p21 general purpose input/output port. this function becomes valid when the settin g of the external trigger input of a/d converter 2 or the setting of the input capture trigger input is set to disabled. 36 pwi0 d pulse width counter input of pwc timer 0 this function becomes valid when pulse widt h counter input of pwc timer 0 is set to enabled. p22 general purpose input/output port. this function becomes valid when pulse widt h counter input of pwc timer 0 is set to disabled.
mb91265a series 8 (continued) pin no. pin name i/o circuit type* 1 description 37 dtti d control input signal of multi-function time r waveform generator output rto0 to rto5. this function becomes valid w hen dtti input is set to enabled. p23 general purpose input/output port. this function becomes valid when in put of dtti is set to disabled. 38 cki d external clock input terminal of free-run timer. since this input is used as required while the port is used for external clock input terminal of free-run timer, the port output must remain off unless intentionally used. p24 general purpose input/output port. this function becomes valid when external clock input of free-run timer is set to disabled. 39 ic0 d trigger input terminal of input capture 0. the port can serve as an input when set for i nput with the setting of the trigger input of input capture 0. when the port is used for input capture input, this input is used as required. the port output must therefor e remain off unless intentionally used. p25 general purpose input/output port. this function becomes valid when trigger i nput of input capture 0 is set to disabled. 40 ic1 d trigger input terminal of input capture 1. the port can serve as an input when set for i nput with the setting of the trigger input of input capture 1. when the port is used for input capture input, this input is used as required. the port output must therefor e remain off unless intentionally used. p26 general purpose input/output port. this function becomes valid when trigger inpu t of input capture 1 is set to disabled. 41 p27 d general purpose input/output port. 42 ppg0 d output terminal of ppg timer 0. this function becomes valid when output of ppg timer 0 is set to enabled. pg1 general purpose input/output port. this function becomes valid when output of ppg timer 0 is set to disabled. 43 md2 h, k mode terminal 2. setting this pin determines the basi c operation mode. connect to v cc or v ss . the circuit type of flash memory models is k. 44 md1 h, k mode terminal 1. setting this pin determines the basi c operation mode. connect to v cc or v ss . the circuit type of flash memory models is k. 45 md0 h mode terminal 0. setting this pin determines the basi c operation mode. connect to v cc or v ss . 46 x0 a clock (oscillation) input terminal. 47 x1 a clock (oscillation) output terminal. 49 ppg4 d output terminal of ppg timer 4. this function becomes valid when output of ppg timer 4 is set to enabled. p37 general purpose input/output port. this function becomes valid when output of ppg timer 4 is set to disabled.
mb91265a series 9 (continued) pin no. pin name i/o circuit type* 1 description 50 int7 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. ppg7 output terminal of ppg timer 7. this function becomes valid when outp ut of ppg timer 7 is set to enabled. p36 general purpose input/output port. this function becomes valid when output of ppg timer 7 is set to disabled. 51 init i external reset input terminal. 52 rto5 j waveform generator output termin al of multi-function timer. this terminal outputs waveform set at the waveform generator. this function becomes valid when waveform generator output of multi-function timer is set to enabled. p35 general purpose input/output port. this function becomes valid when output of waveform generator is set to disabled. 53 rto4 j waveform generator output termin al of multi-function timer. this terminal outputs waveform set at the waveform generator. this function becomes valid when waveform generator output of multi-function timer is set to enabled. p34 general purpose input/output port. this function becomes valid when output of waveform generator is set to disabled. 54 rto3 j waveform generator output termin al of multi-function timer. this terminal outputs waveform set at the waveform generator. this function becomes valid when waveform generator output of multi-function timer is set to enabled. p33 general purpose input/output port. this function becomes valid when output of waveform generator is set to disabled. 55 rto2 j waveform generator output termin al of multi-function timer. this terminal outputs waveform set at the waveform generator. this function becomes valid when waveform generator output of multi-function timer is set to enabled. p32 general purpose input/output port. this function becomes valid when output of waveform generator is set to disabled. 56 rto1 j waveform generator output termin al of multi-function timer. this terminal outputs waveform set at the waveform generator. this function becomes valid when waveform generator output of multi-function timer is set to enabled. p31 general purpose input/output port. this function becomes valid when output of waveform generator is set to disabled. 57 rto0 j waveform generator output termin al of multi-function timer. this terminal outputs waveform set at the waveform generator. this function becomes valid when waveform generator output of multi-function timer is set to enabled. p30 general purpose input/output port. this function becomes valid when output of waveform generator is set to disabled. 58 int0 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. p40 general purpose input/output port. this function becomes valid when exter nal interrupt input is set to disabled.
mb91265a series 10 (continued) *1 : for the i/o circuit type, refer to ? i/o circuit type ? *2 : c-can is set in only MB91F267NA. ? power supply and gnd pins pin no. pin name i/o circuit type* 1 description 59 int1 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. p41 general purpose input/output port. this function becomes valid when exter nal interrupt input is set to disabled. 60 int2 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. p42 general purpose input/output port. this function becomes valid when exter nal interrupt input is set to disabled. 61 int3 e external interrupt input terminal. since this input is used as required while the corresponding external interrupt is enabled, the port output must remain off unless intentionally used. p43 general purpose input/output port. this function becomes valid when exter nal interrupt input is set to disabled. pin no. pin name description 16, 48 vss gnd pins. apply equal potential to all of the pins. 17 vcc power supply pin. apply equal potential to all of the pins. 64 avcc analog power supply pin for a/d converter. 63 avrh2 analog reference power supply pin for a/d converter 2. 62 avrh1 analog reference power supply pin for a/d converter 1. 1 avss analog gnd pin for a/d converter. 15 c condenser connection pin for internal regulator. 2 acc condenser connection pin for analog.
mb91265a series 11 i/o circuit type (continued) type circuit type remarks a oscillation feedback resistance for high speed (main clock oscillation) : approx. 1 m ? d cmos level output cmos level hysteresis input with standby control with pull-up control i ol = 4 ma e cmos level output cmos level hysteresis input without standby control with pull-up control i ol = 4 ma x1 x0 clock input standby control p-ch p-ch n-ch digital input pull-up control digital output digital output standby control p-ch n-ch p-ch digital input digital output digital output pull-up control
mb91265a series 12 (continued) type circuit type remarks g analog/cmos level hysteresis input/output pin cmos level output cmos level hysteresis input (attached with standby control) analog input (analog input is enabled when aicr?s corresponding bit is set to ?1?.) i ol = 4 ma h cmos level hysteresis input without standby control i cmos level hysteresis input with pull-up resistor without standby control p-ch n-ch analog input digital input digital output digital output standby control n-ch p-ch digital input p-ch p-ch n-ch digital input
mb91265a series 13 (continued) type circuit type remarks j cmos level output cmos level hysteresis input with standby control i ol = 12 ma k flash memory product only cmos level input high voltage control for test of flash p-ch n-ch digital output digital output digital input standby control n-ch n-ch n-ch n-ch n-ch mode input control signal
mb91265a series 14 handling devices preventing latch-up latch-up may occur in a cmos ic if a voltage greater than v cc pin or less than v ss pin is applied to an input or output pin or if an above-rati ng voltage is applied between v cc and v ss pins. a latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. when you use a cmos ic, be very ca reful not to exceed the absolute maximum rating. treatment of unused input pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull- up or pull-down resistor. about power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss pins near this device. about crystal oscillator circuit noise near the x0 and x1 pins may cause the device to malfunction. design the printed circuit board so that x0 and x1 pins the crystal oscillator (or ceramic oscilla tor) , and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board ar twork with the x0 and x1 pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillatio nal characteristics of the crystal and this device. about mode pins (md0 to md2) these pins should be connected directly to v cc or v ss pins. to prevent the device erroneously switching to test mode due to noise, design the pr inted circuit board such that the distance between the mode pins and v cc or v ss pins is as short as possib le and the connection impedance is low. operation at start-up be sure to execute setting init ialized reset (init) with init pin immediately after start-up. also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up, hold the ?l? level input to the init pin for the required stabilization wait time (for init via the init pin, the oscillation stabilization wait time setting is initialized to the minimum value) .
mb91265a series 15 order of power turning on/off use the following procedure for turning the power on or off. note that, even if the a/d converter is not used, keep the following pins connected with the level as described below. av cc = v cc level av ss = v ss level when powering on : v cc av cc avrh when powering off : avrh av cc v cc about oscillation input at power on when turning the power on, maintain clock input until t he device is released from the oscillation stabilization wait state.
mb91265a series 16 caution for operation during pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll may c ontinue its operation at its self-running frequency. however, fujitsu will not guaran tee results of operations if such failure occurs. external clock when external clock is selected, the opposite phase clock to x0 pin must be supplied to x1 pin simultaneously. if the stop mode (oscillation stop mode) is used simult aneously, the x1 pin is stopped with the "h" output. so, when stop mode is specified, approximately 1 k ? of resistance should be added ex ternally to avoid the collision of output. the following figure shows using an external clock. c pin a bypass capacitor of approximately 0.1 f should be connected the c pin for built-in regulator. acc pin a capacitor of approximately 0.1 f should be inserted between the acc pin and the av ss pin as this product has built-in a/d converter. x0 x1 using an external clock mb91265a series c 0.1 f gnd v ss mb91265a series acc 0.1 f av ss mb91265a series
mb91265a series 17 clock control block input the ?l? signal to the init pin to assure the clock oscillation stabilization wait time. switch shared port function to switch between the use as a port and the use as a dedicated pin, use the port function register (pfr) . low power consumption mode to enter the standby mode, use the syn chronous standby mode (set with the syncs bit as bit 8 in the tbcr : timebase counter control register) and be sure to use the following sequence in addition, please set i flag, ilm, and icr to diverge to the interruption handler that is the return factor after the standby returns. please do not do the following wh en the monitor debugger is used. break point setting for above instruction lines step execution for above instruction lines (ldi #value_of_standby, r0) : va lue_of_standby is write data to stcr. (ldi #_stcr, r12) : _stcr is address (481 h ) of stcr. stb r0, @r12 : writing to standby control register (stcr) ldub @r12, r0 : st cr read for synchronous standby ldub @r12, r0 : dummy re-read of stcr nop : nop 5 for arrangement of timing nop nop nop nop
mb91265a series 18 notes on the ps register as the ps register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the ps register to be updated. as the microcontroller is designed to carry out reprocessing correctly upon re turning from such an eit event, it performs operations before and after the eit as specified in either case. the following operations may be performed when t he instruction immediately followed by a divou/divos instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event or emulator menu : 1) the d0 and d1 flags are updated in advance. 2) an eit handling routine (user in terrupt or emulator) is executed. 3) upon returning from the eit, the divou/divos instru ction is executed, and the d0 and d1 flags are updated to the same values as in 1). the following operations are performed when the orccr/stilm/movri and ps instructions are executed to allow the interrupt. 1) the ps register is updated in advance. 2) an eit handling routine (user interrupt) is executed. 3) upon returning from the eit, the above instructions are executed, and the ps register is updated to the same value as in 1). watchdog timer the watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. the watchdog timer resets the cpu if the program runs out of controls, preventing the reset defer function from being executed. once the function of the watchdog timer is enabled, t herefore, the watchdog timer keeps on operating programs until it resets the cpu. as an exception, the watchdog timer defers a reset autom atically under the condition in which the cpu stops program execution. for those conditions to which this exception applies, refer to ? note on debugger?.
mb91265a series 19 note on debugger ? step execution of reti command if an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. this will prevent the main routine and low-in terrupt-level programs from being executed. do not execute step of reti instruction for escape. disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine no longer needs debugging. ? operand break do not apply a data event break to access to the area containing the address of a system stack pointer. ? execution in an unused area of flash memory accidentally executing an instruction in an unused area of flash memory (with data placed at 0xffff) prevents breaks from being accepted. to prevent this, the code event address mask function of the debugger should be used to cause a break when accessing an instruction in an unused area. ? power-on debugging all of the following three conditions must be satisfied wh en the power supply is turned off by power-on debugging. (1) the time for the user power to fall from 0.9 v cc to 0.5 v cc is 25 s or longer. note : in a dual-power system, v cc indicates the external i/o power supply voltage. (2) cpu operating frequency must be higher than 1 mhz. (3) during execution of user program ? interrupt handler for nmi request (tool) add the following program to the interrupt handler to prev ent the device from malfunctioning in case the factor flag to be set only in response to a br eak request from the ice is set, for ex ample, by an adverse effect of noise to the dsu pin while the ice is not connected. en able to use the ice while adding this program. additional location next interrupt handler additional program interrupt source : nmi request (tool) interrupt number : #13 (decimal) , 0d (hexadecimal) offset : 3c8 h address tbr is default : 000fffc8 h stm (r0, r1) ldi #b00 h , r0; : b00 h is the address of dsu break factor register. ldi #0, r1 stb r1, @r0 : clear the break factor register. ldm (r0, r1) reti
mb91265a series 20 block diagram x0, x1 md0 to md2 init int0 to int7 nmi s in0, s in1 s ot0, s ot1 s ck0, s ck1 av cc adtg1 avrh1 adtg2 avrh2 port tin0 to tin2 tot1, tot2 pwi0 ppg0 to ppg7 cki ic0 to ic 3 rto0 to rto5 dtti 3 2 3 2 16 3 2 an0 to an 3 an4 to an10 tx0 rx0 bit search module 16-bit mac clock control interrupt controller 8 channels external interrupt 2 channels u-timer fr60 lite cpu core bus converter port i/f 3 channels 16-bit reload timer 4 channels 16-bit/ 8 channels 8-bit ppg timer 16-bit free-run timer 3 channels input capture 4 channels output compare 6 channels waveform generator multi-function timer 4 channels input 8/10-bit a/d converter-1 7 channels input 8/10-bit a/d converter-2 16-bit ? 32-bit adapter 1 channel 16-bit pwc timer dmac 5 channels rom 64 kbytes/ flash 128 kbytes ram 2 kbytes/ ram 4 kbytes 2 channels uart timing generator 1 channel c-can (built-in MB91F267NA only)
mb91265a series 21 memory space 1. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. direct addressing areas the following address space ar eas are used as i/o areas. these areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. the size of directly addressable areas depends on the data size to be being accessed as follows. byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h 2. memory map 000f 0000 h 0000 0000 h 0000 0400 h 0001 0000 h 000 3 f 8 00 h 0004 0000 h 0010 0000 h ffff ffff h i/o i/o acce ss di sa llowed intern a l ram 2 k b yte s acce ss di sa llowed intern a l rom 64 k b yte s acce ss di sa llowed single chip mode refer to i/o map direct addressing area mb91266a 000e 0000 h 0000 0000 h 0000 0400 h 0001 0000 h 000 3 f000 h 0004 0000 h 0010 0000 h ffff ffff h i/o i/o acce ss di sa llowed intern a l ram 4 k b yte s acce ss di sa llowed intern a l rom 12 8 k b yte s acce ss di sa llowed single chip mode refer to i/o map direct addressing area mb91f267a/MB91F267NA
mb91265a series 22 mode settings the fr family uses mode pins (md2 to md 0) and a mode data to se t the operation mode. mode pins the md2 to md0 pins specify how the mode vect or fetch and reset vector fetch is performed. setting is prohibited other than that shown in the following table. mode data data written to the internal mode register (m odr) by a mode vector fetch is called mode data. after an operation mode has been set in the mode register, the device operates in the operation mode. the mode data is set by all reset source. user programs cannot set data to the mode register. details of mode data description bit31 to bit24 are all reserved bits. be sure to set this bit to ?00000111?. operation is not guaranteed when an y value other than ?00000111? is set. note : mode data set in the mode vector mu st be placed as byte data at 0x000ffff8 h . use the highest byte from bit31 to bit24 for placemen t as the fr family uses the big endian for byte endian. mode pins mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal 0 0 1 external rom mode vector extern al not supported by this model. 3 1 b it 3 0292 8 27 26 25 24 00000111 operation mode setting bits 31 bit 24 23 16 15 8 7 0 xxxxxxxx 0x000ffff8 h 0x000ffff8 h 0x000ffffc h xxxxxxxx xxxxxxxx mode data mode data reset vector xxxxxxxx xxxxxxxx xxxxxxxx incorrect correct
mb91265a series 23 i/o map [how to read the table] note : initial values of register bits are represented as follows : ? 1 ? : initial value ? 1 ? ? 0 ? : initial value ? 0 ? ? x ? : initial value ? undefined? ? - ? : no physical register at this location access is barred with an un defined data access attribute. address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register read/write attribute access unit (b : byte, h : half word, w : word) initial value of register after reset register name (column 1 of the regist er is at address 4n, column 2 is at address 4n + 1...) leftmost register address (for wo rd-length access, column 1 of the register becomes the msb of the data.)
mb91265a series 24 (continued) address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b, h, w xxxxxxxx pdr1 [r/w] b, h, w xxxxxxxx pdr2 [r/w] b, h, w xxxxxxxx pdr3 [r/w] b, h, w xxxxxxxx port data register 000004 h pdr4 [r/w] b, h, w -xxxxxxx pdr5 [r/w] b, h, w xxxxxxxx ?? 000008 h ???? 00000c h ???? 000010 h pdrg [r/w] b, h, w ------x- ??? 000014 h to 00003c h ? reserved 000040 h eirr0 [r/w] b, h, w 00000000 enir0 [r/w] b, h, w 00000000 elvr0 [r/w] b, h, w 00000000 00000000 external interrupt (int0 to int7) 000044 h dicr [r/w] b, h, w -------0 hrcl [r/w, r] b, h, w 0--11111 ?? delay interrupt/ hold request 000048 h tmrlr0 [w] h, w xxxxxxxx xxxxxxxx tmr0 [r] h, w xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w, r] b, h, w ---00000 00000000 000050 h tmrlr1 [w] h, w xxxxxxxx xxxxxxxx tmr1 [r] h, w xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w, r] b, h, w ---00000 00000000 000058 h tmrlr2 [w] h, w xxxxxxxx xxxxxxxx tmr2 [r] h, w xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r/w, r] b, h, w ---00000 00000000 000060 h ssr0 [r/w, r] b, h, w 00001000 sidr0 [r]/sodr0[w] b, h, w xxxxxxxx scr0 [r/w] b, h, w 00000100 smr0 [r/w, w] b, h, w 00--0-0- uart0 000064 h utim0 [r] h / utimr0 [w] h 00000000 00000000 drcl0 [w] b -------- utimc0 [r/w] b 0--00001 u-timer 0 000068 h ssr1 [r/w, r] b, h, w 00001000 sidr1 [r]/sodr1[w] b, h, w xxxxxxxx scr1 [r/w] b, h, w 00000100 smr1 [r/w] b, h, w 00--0-0- uart1 00006c h utim1 [r] h / utimr1 [w] h 00000000 00000000 drcl1 [w] b -------- utimc1 [r/w] b 0--00001 u-timer 1 000070 h to 00007c h ???? reserved
mb91265a series 25 (continued) address register block + 0 + 1 + 2 + 3 000080 h adch1 [r/w] b, h, w xxxx0xx0 admd1 [r/w] b, h, w 00001111 adcd11 [r] b, h, w xxxxxxxx adcd10 [r] b, h, w xxxxxxxx a/d converter 1/ aicr1 000084 h adcs1 [r/w, w] b, h, w 00000x00 ? aicr1 [r/w] b, h, w ----0000 ? 000088 h adch2 [r/w] b, h, w xxxx0xx0 admd2 [r/w] b, h, w 00001111 adcd21 [r] b, h, w xxxxxxxx adcd20 [r] b, h, w xxxxxxxx a/d converter 2/ aicr2 00008c h adcs2 [r/w, w] b, h, w 00000x00 ? aicr2 [r/w] b, h, w -0000000 ? 000090 h occpbh0, occpbl0[w] / occph0, occpl0[r] h, w 00000000 00000000 occpbh1, occpbl1[w] / occph1, occpl1 [r] h, w 00000000 00000000 16-bit output compare 000094 h occpbh2, occpbl2[w] / occph2, occpl2 [r] h, w 00000000 00000000 occpbh3, occpbl3[w] / occph3, occpl3 [r] h, w 00000000 00000000 000098 h occpbh4, occpbl4[w] / occph4, occpl4 [r] h, w 00000000 00000000 occpbh5, occpbl5[w] / occph5, occpl5 [r] h, w 00000000 00000000 00009c h ocsh1 [r/w] b, h, w x1100000 ocsl0 [r/w] b, h, w 00001100 ocsh3 [r/w] b, h, w x1100000 ocsl2 [r/w] b, h, w 00001100 0000a0 h ocsh5 [r/w] b, h, w x1100000 ocsl4 [r/w] b, h, w 00001100 ocmod [r/w] b, h, w xx000000 ? 0000a4 h cpclrbh0, cpclrbl0[w]/ cpclrh0, cpclrl0[r] h, w 11111111 11111111 tcdth0, tcdtl0 [r/w] h, w 00000000 00000000 16-bit free-run timer 0 0000a8 h tccsh0 [r/w] b, h, w 00000000 tccsl0 [r/w] b, h, w 01000000 ? adtrgc [r/w] b, h, w xxxx0000 0000ac h ipcph0, ipcpl0 [r] h, w xxxxxxxx xxxxxxxx ipcph1, ipcpl1 [r] h, w xxxxxxxx xxxxxxxx 16-bit input capture 0000b0 h ipcph2, ipcpl2 [r] h, w xxxxxxxx xxxxxxxx ipcph3, ipcpl3 [r] h, w xxxxxxxx xxxxxxxx 0000b4 h picsh01 [w] b, h, w 00000000 picsl01 [r/w] b, h, w 00000000 icsh23 [r] b, h, w xxxxxx00 icsl23 [r/w]b, h, w 00000000 0000b8 h ???? reserved 0000bc h tmrrh0, tmrrl0 [r/w] h, w xxxxxxxx xxxxxxxx tmrrh1, tmrrl1 [r/w] h, w xxxxxxxx xxxxxxxx waveform generator 0000c0 h tmrrh2, tmrrl2 [r/w] h, w xxxxxxxx xxxxxxxx ?? 0000c4 h dtcr0 [r/w] b, h, w 00000000 dtcr1 [r/w] b, h, w 00000000 dtcr2 [r/w] b, h, w 00000000 ? 0000c8 h ? sigcr1 [r/w] b, h, w 00000000 ? sigcr2 [r/w] b, h, w xxxxxxx1
mb91265a series 26 (continued) address register block + 0 + 1 + 2 + 3 0000cc h ? adcomp1 [r/w] h, w 00000000 00000000 a/d comp 0000d0 h adcomp2 [r/w] h, w 00000000 00000000 adcompc2 [r/w] b, h, w xx0000xx adcompc1 [r/w] b, h, w xxxxx00x 0000d4 h ???? reserved 0000d8 h ???? 0000dc h ???? 0000e0 h pwcsr0 [r/w, r] b, h, w 00000000 00000000 pwcr0 [r] h, w 00000000 00000000 16-bit pwc timer 0000e4 h ???? 0000e8 h ? pdivr0 [r/w] b, h, w xxxxx000 ?? 0000ec h ???? reserved 0000f0 h ???? 000f4 h to 000fc h ???? 000100 h prlh0 [r/w] b, h, w xxxxxxxx prll0 [r/w] b, h, w xxxxxxxx prlh1 [r/w] b, h, w xxxxxxxx prll1 [r/w] b, h, w xxxxxxxx 8/16-bit ppg timer 0 to 7 000104 h prlh2 [r/w] b, h, w xxxxxxxx prll2 [r/w] b, h, w xxxxxxxx prlh3 [r/w] b, h, w xxxxxxxx prll3 [r/w] b, h, w xxxxxxxx 000108 h ppgc0 [r/w] b, h, w 00000000 ppgc1 [r/w] b, h, w 00000000 ppgc2 [r/w] b, h, w 00000000 ppgc3 [r/w] b, h, w 00000000 00010c h prlh4 [r/w] b, h, w xxxxxxxx prll4 [r/w] b, h, w xxxxxxxx prlh5 [r/w] b, h, w xxxxxxxx prll5 [r/w] b, h, w xxxxxxxx 000110 h prlh6 [r/w] b, h, w xxxxxxxx prll6 [r/w] b, h, w xxxxxxxx prlh7 [r/w] b, h, w xxxxxxxx prll7 [r/w] b, h, w xxxxxxxx 000114 h ppgc4 [r/w] b, h, w 00000000 ppgc5 [r/w] b, h, w 00000000 ppgc6 [r/w] b, h, w 00000000 ppgc7 [r/w] b, h, w 00000000 000118 h to 00012c h ???? reserved 000130 h trg [r/w] b, h, w -------- 00000000 ? gatec [r/w] b, h, w xxxxxx00 8/16-bit ppg timer 0 to 7 000134 h revc [r/w] b, h, w -------- 00000000 ?? 000138 h to 000140 h ???? reserved
mb91265a series 27 (continued) address register block + 0 + 1 + 2 + 3 000144 h ttcr0 [r/w] b, h, w 00000000 ?? tstpr0 [r] b, h, w 00000000 timing generator 000148 h comp0 [r/w] b, h, w 00000000 comp2 [r/w] b, h, w 00000000 comp4 [r/w] b, h, w 00000000 comp6 [r/w] b, h, w 00000000 00014c h ???? 000150 h ???? 000154 h cpclrbh1, cpclrbl1 [w] / cpclrh1, cpclrl1 [r] h, w 11111111 11111111 tcdth1, tcdtl1 [r/w] h, w 00000000 00000000 16-bit free-run timer 1 000158 h tccsh1 [r/w] b, h, w 00000000 tccsl1 [r/w] b, h, w 01000000 ?? 00015c h cpclrbh2, cpclrbl2 [w] / cpclrh2, cpclrl2 [r] h, w 11111111 11111111 tcdth2, tcdtl2 [r/w] h, w 00000000 00000000 16-bit free-run timer 2 000160 h tccsh2 [r/w] b, h, w 00000000 tccsl2 [r/w] b, h, w 01000000 ?? 000164 h ???? reserved 000168 h ? fsr2 [r/w] b, h, w 00000000 fsr1 [r/w] b, h, w ----0000 fsr0 [r/w] b, h, w 00000000 frt selector 00016c h to 0001a4 h ? reserved 0001a8 h canpre [r, r/w] b, h, w 00000000 ??? c-can* 1 prescaler 0001ac h to 0001fc h ? reserved 000200 h dmaca0 [r/w] b, h, w * 2 00000000 0000 xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000208 h dmaca1 [r/w] b, h, w* 2 00000000 0000 xxxx xxxxxxxx xxxxxxxx 00020c h dmacb1 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] b, h, w * 2 00000000 0000 xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] b, h, w * 2 00000000 0000 xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] b, h, w * 2 00000000 0000 xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] b, h, w 00000000 00000000 xxxxxxxx xxxxxxxx
mb91265a series 28 (continued) address register block + 0 + 1 + 2 + 3 000228 h to 00023c h ? reserved 000240 h dmacr [r/w] b 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac 000244 h to 00024c h ? reserved 000250 h ??? ? 000254 h to 000398 h ? 00039c h ??? ? 16 bit mac 0003a0 h dsp-pc [r/w] xxxxxxxx dsp-csr [r/w, r, w] 00000000 dsp-ly [r/w] xxxxxxxx xxxxxxxx 0003a4 h dsp-ot0 [r] xxxxxxxx xxxxxxxx dsp-ot1 [r] xxxxxxxx xxxxxxxx 0003a8 h dsp-ot2 [r] xxxxxxxx xxxxxxxx dsp-ot3 [r] xxxxxxxx xxxxxxxx 0003ac h ??? ? 0003b0 h dsp-ot4 [r] xxxxxxxx xxxxxxxx dsp-ot5 [r] xxxxxxxx xxxxxxxx 0003b4 h dsp-ot6[r] xxxxxxxx xxxxxxxx dsp-ot7 [r] xxxxxxxx xxxxxxxx 0003b8 h ??? ? 0003bc h to 0003ec h ? reserved 0003f0 h bsd0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] b, h, w 00000000 ddr1 [r/w] b, h, w 00000000 ddr2 [r/w] b, h, w 00000000 ddr3 [r/w] b, h, w 00000000 data direction register 000404 h ddr4 [r/w] b, h, w -0000000 ddr5 [r/w] b, h, w 00000000 ?? 000408 h ??? ? 00040c h ??? ? 000410 h ddrg [r/w] b, h, w ------0- ?? ?
mb91265a series 29 (continued) address register block + 0 + 1 + 2 + 3 000414 h to 00041c h ? reserved 000420 h pfr0 [r/w] b, h, w 00------ pfr1 [r/w] b, h, w 0-0-00-0 ?? port function register 000424 h ??? ? 000428 h ??? ? 00042c h ??? ? 000430 h ??? ptfr0 [r/w] b, h, w 00000000 000434 h to 00043c h ? reserved 000440 h icr00 [r/w, r] b, h, w ----1111 icr01 [r/w, r] b, h, w ----1111 icr02 [r/w, r] b, h, w ----1111 icr03 [r/w, r] b, h, w ----1111 interrupt control unit 000444 h icr04 [r/w, r] b, h, w ----1111 icr05 [r/w, r] b, h, w ----1111 icr06 [r/w, r] b, h, w ----1111 icr07 [r/w, r] b, h, w ----1111 000448 h icr08 [r/w, r] b, h, w ----1111 icr09 [r/w, r] b, h, w ----1111 icr10 [r/w, r] b, h, w ----1111 icr11 [r/w, r] b, h, w ----1111 00044c h icr12 [r/w, r] b, h, w ----1111 icr13 [r/w, r] b, h, w ----1111 icr14 [r/w, r] b, h, w ----1111 icr15 [r/w, r] b, h, w ----1111 000450 h icr16 [r/w, r] b, h, w ----1111 icr17 [r/w, r] b, h, w ----1111 icr18 [r/w, r] b, h, w ----1111 icr19 [r/w, r] b, h, w ----1111 000454 h icr20 [r/w, r] b, h, w ----1111 icr21 [r/w, r] b, h, w ----1111 icr22 [r/w, r] b, h, w ----1111 icr23 [r/w, r] b, h, w ----1111 000458 h icr24 [r/w, r] b, h, w ----1111 icr25 [r/w, r] b, h, w ----1111 icr26 [r/w, r] b, h, w ----1111 icr27 [r/w, r] b, h, w ----1111 00045c h icr28 [r/w, r] b, h, w ----1111 icr29 [r/w, r] b, h, w ----1111 icr30 [r/w, r] b, h, w ----1111 icr31 [r/w, r] b, h, w ----1111 000460 h icr32 [r/w, r] b, h, w ----1111 icr33 [r/w, r] b, h, w ----1111 icr34 [r/w, r] b, h, w ----1111 icr35 [r/w, r] b, h, w ----1111 000464 h icr36 [r/w, r] b, h, w ----1111 icr37 [r/w, r] b, h, w ----1111 icr38 [r/w, r] b, h, w ----1111 icr39 [r/w, r] b, h, w ----1111 000468 h icr40 [r/w, r] b, h, w ----1111 icr41 [r/w, r] b, h, w ----1111 icr42 [r/w, r] b, h, w ----1111 icr43 [r/w, r] b, h, w ----1111 00046c h icr44 [r/w, r] b, h, w ----1111 icr45 [r/w, r] b, h, w ----1111 icr46 [r/w, r] b, h, w ----1111 icr47 [r/w, r] b, h, w ----1111 000470 h to 00047c h ? reserved
mb91265a series 30 (continued) address register block + 0 + 1 + 2 + 3 000480 h rsrr [r/w] b, h, w 10000000 stcr [r/w] b, h, w 00110011 tbcr [r/w] b, h, w 00xxxx00 ctbr [w] b, h, w xxxxxxxx clock control 000484 h clkr [r/w] b, h, w 00000000 wpr [w] b, h, w xxxxxxxx divr0 [r/w] b, h, w 00000011 divr1 [r/w] b, h, w 00000000 000488 h ??? ? 00048c h ??? ? 000490 h ??? ? 000494 h to 0005fc h ? reserved 000600 h pcr0 [r/w] b, h, w 00000000 pcr1 [r/w] b, h, w 00000000 pcr2 [r/w] b, h, w 00000000 pcr3 [r/w] b, h, w 00------ pull-up control unit 000604 h pcr4 [r/w] b, h, w ----0000 ?? ? 000608 h ??? ? 00060c h ??? ? 000610 h pcrg [r/w] b, h, w ------0- ?? ? 000614 h to 00063c h ? reserved 000640 h to 000ffc h ? 001000 h dmasa0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91265a series 31 (continued) address register block + 0 + 1 + 2 + 3 001028 h to 006ffc h ? reserved 007000 h flcr [r/w] b 01101000 ?? ? flash 007004 h flwc [r/w] b 00000011 ?? ? 007008 h ?? ? ? 00700c h ?? ? ? 007010 h ?? ? ? 007014 h to 00bffc h ? reserved 00c000 h to 00c07c h x-ram (coefficient ram) [r/w] 64 16-bit 16 bit mac 00c080 h to 00c0fc h y-ram (variable ram) [r/w] 64 16-bit 00c100 h to 00c2fc h i-ram (instruction ram) [r/w] 256 16-bit 00c300 h to 00fffc h ? reserved 020000 h ctrlr0 [r, r/w] 00000000 00000001 statr0 [r, r/w] 00000000 00000000 c-can* 1 020004 h errcnt0 [r] 00000000 00000000 btr0 [r, r/w] 00100011 00000001 020008 h intr0 [r] 00000000 00000000 testr0 [r, r/w] 00000000 x0000000 02000c h brper0 [r, r/w] 00000000 00000000 ?? 020010 h if1creq0 [r, r/w] 00000000 00000000 if1cmsk0 [r, r/w] 00000000 00000000 020014 h if1msk20 [r, r/w] 11111111 11111111 if1msk10 [r/w] 11111111 11111111 020018 h if1arb20 [r/w] 00000000 00000000 if1arb10 [r/w] 00000000 00000000 02001c h if1mctr0 [r, r/w] 00000000 00000000 ?? 020020 h if1dta10 [r/w] 00000000 00000000 if1dta20 [r/w] 00000000 00000000 020024 h if1dtb10 [r/w] 00000000 00000000 if1dtb20 [r/w] 00000000 00000000
mb91265a series 32 (continued) *1 : c-can is loaded in only MB91F267NA. *2 : the lower 16 bits (dtc15 to dtc0) of dm aca0 to dmaca4 cannot be accessed in bytes. notes : ? the initial value of flwc (7004 h ) is ?00010011 b ? on eva tool. writing ?00000011 b ? on the evaluation model has no effect on its operation. ? do not execute read modify write instructio ns on registers having a write-only bit. ? data is undefined in reserved or (-) area. address register block + 0 + 1 + 2 + 3 020030 h reserved (if1 data mirror, little endian byte ordering) c - can* 1 020040 h if2creq0 [r, r/w] 00000000 00000000 if2cmsk0 [r, r/w] 00000000 00000000 020044 h if2msk20 [r, r/w] 11111111 11111111 if2msk10 [r/w] 11111111 11111111 020048 h if2arb20 [r/w] 00000000 00000000 if2arb10 [r/w] 00000000 00000000 02004c h if2mctr0 [r, r/w] 00000000 00000000 ?? 020050 h if2dta10 [r/w] 00000000 00000000 if2dta20 [r/w] 00000000 00000000 020054 h if2dtb10 [r/w] 00000000 00000000 if2dtb20 [r/w] 00000000 00000000 020060 h reserved (if2 data mirror, little endian byte ordering) 020080 h treqr20 [r] 00000000 00000000 treqr10 [r] 00000000 00000000 020084 h reserved (>32..128 message buffer) 020090 h newdt20 [r] 00000000 00000000 newdt10 [r] 00000000 00000000 020094 h reserved (>32..128 message buffer) 0200a0 h intpnd20 [r] 00000000 00000000 intpnd10 [r] 00000000 00000000 0200a4 h reserved (>32..128 message buffer) 0200b0 h mesval20 [r] 00000000 00000000 mesval10 [r] 00000000 00000000 0200b4 h reserved (>32..128 message buffer)
mb91265a series 33 interrupt vector (continued) interrupt source interrupt number interrupt level offset tbr default address decimal hexa- decimal reset 0 00 ? 3fc h 000ffffc h mode vector 1 01 ? 3f8 h 000ffff8 h system reserved 2 02 ? 3f4 h 000ffff4 h system reserved 3 03 ? 3f0 h 000ffff0 h system reserved 4 04 ? 3ec h 000fffec h system reserved 5 05 ? 3e8 h 000fffe8 h system reserved 6 06 ? 3e4 h 000fffe4 h coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h coprocessor error trap 8 08 ? 3dc h 000fffdc h inte instruction 9 09 ? 3d8 h 000fffd8 h system reserved 10 0a ? 3d4 h 000fffd4 h system reserved 11 0b ? 3d0 h 000fffd0 h step trace trap 12 0c ? 3cc h 000fffcc h nmi request (tool) 13 0d ? 3c8 h 000fffc8 h undefined instruction exception 14 0e ? 3c4 h 000fffc4 h nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h external interrupt 4 20 14 icr04 3ac h 000fffac h external interrupt 5 21 15 icr05 3a8 h 000fffa8 h external interrupt 6/c-can wake up* 22 16 icr06 3a4 h 000fffa4 h external interrupt 7 23 17 icr07 3a0 h 000fffa0 h reload timer 0 24 18 icr08 39c h 000fff9c h reload timer 1 25 19 icr09 398 h 000fff98 h reload timer 2 26 1a icr10 394 h 000fff94 h uart0(reception completed) 27 1b icr11 390 h 000fff90 h uart0 (rx completed) 28 1c icr12 38c h 000fff8c h dtti 29 1d icr13 388 h 000fff88 h dmac0 (end, error) 30 1e icr14 384 h 000fff84 h dmac1 (end, error) 31 1f icr15 380 h 000fff80 h dmac2/dmac3/dmac4 (end, error) 32 20 icr16 37c h 000fff7c h
mb91265a series 34 (continued) interrupt source interrupt number interrupt level offset tbr default address decimal hexa- decimal uart1(reception completed) 33 21 icr17 378 h 000fff78 h uart1 (rx completed) 34 22 icr18 374 h 000fff74 h c-can0* 35 23 icr19 370 h 000fff70 h system reserved 36 24 icr20 36c h 000fff6c h 16-bit mac 37 25 icr21 368 h 000fff68 h ppg0/ppg1 38 26 icr22 364 h 000fff64 h ppg2/ppg3 39 27 icr23 360 h 000fff60 h ppg4/ppg5/ppg6/ppg7 40 28 icr24 35c h 000fff5c h system reserved 41 29 icr25 358 h 000fff58 h waveform0/1/2 (underflow) 42 2a icr26 354 h 000fff54 h free-run timer 1 (compare clear) 43 2b icr27 350 h 000fff50 h free-run timer 1 (zero detection) 44 2c icr28 34c h 000fff4c h free-run timer 2 (compare clear) 45 2d icr29 348 h 000fff48 h free-run timer 2 (zero detection) 46 2e icr30 344 h 000fff44 h timebase timer overflow 47 2f icr31 340 h 000fff40 h free-run timer 0 (compare clear) 48 30 icr32 33c h 000fff3c h free-run timer 0 (zero detection) 49 31 icr33 338 h 000fff38 h system reserved 50 32 icr34 334 h 000fff34 h a/d converter 1 51 33 icr35 330 h 000fff30 h a/d converter 2 52 34 icr36 32c h 000fff2c h pwc0 (measurement completed) 53 35 icr37 328 h 000fff28 h system reserved 54 36 icr38 324 h 000fff24 h pwc0 (overflow) 55 37 icr39 320 h 000fff20 h system reserved 56 38 icr40 31c h 000fff1c h icu0 (capture) 57 39 icr41 318 h 000fff18 h icu1 (capture) 58 3a icr42 314 h 000fff14 h icu2/3 (capture) 59 3b icr43 310 h 000fff10 h ocu0/1 (match) 60 3c icr44 30c h 000fff0c h ocu2/3 (match) 61 3d icr45 308 h 000fff08 h ocu4/5 (match) 62 3e icr46 304 h 000fff04 h delay interrupt source bit 63 3f icr47 300 h 000fff00 h system reserved (used by realos) 64 40 ? 2fc h 000ffefc h system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h
mb91265a series 35 (continued) * : c-can interrupt is only loaded in MB91F267NA. interrupt source interrupt number interrupt level offset tbr default address decimal hexa- decimal system reserved 66 42 ? 2f4 h 000ffef4 h system reserved 67 43 ? 2f0 h 000ffef0 h system reserved 68 44 ? 2ec h 000ffeec h system reserved 69 45 ? 2e8 h 000ffee8 h system reserved 70 46 ? 2e4 h 000ffee4 h system reserved 71 47 ? 2e0 h 000ffee0 h system reserved 72 48 ? 2dc h 000ffedc h system reserved 73 49 ? 2d8 h 000ffed8 h system reserved 74 4a ? 2d4 h 000ffed4 h system reserved 75 4b ? 2d0 h 000ffed0 h system reserved 76 4c ? 2cc h 000ffecc h system reserved 77 4d ? 2c8 h 000ffec8 h system reserved 78 4e ? 2c4 h 000ffec4 h system reserved 79 4f ? 2c0 h 000ffec0 h used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h
mb91265a series 36 pin status in each cpu state terms used as the status of pins mean as follows. input enabled indicates that the input function can be used. input 0 fixed indicates that the input level has been internally fixe d to be 0 to prevent leakage when the input is released. output hi-z output is maintained. indicates the output in the output state existing immediately before th is mode is established. if the device enters this mode with an internal outp ut peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. state existing immediately before is maintained. when the device serves for output or input immediatel y before entering this mode, the device maintains the output or is ready for the input, respectively. ? list of pin status (single chip mode) (continued) pin no. pin name function at initializing at sleep mode at stop mode init = l* 1 init = h* 2 hi-z = 0 hi-z = 1 3 to 10 p50 to p57 an0 to an7 output hi-z/ input disabled output hi-z/ input enabled retention of the immedi- ately prior state retention of the immediately prior state output hi-z/ input 0 fixed 11 to 13 p44 to p46 an8 to an10 14 nmi nmi input enabled input enabled input enabled input enabled input enabled 18 p00 ppg1/int4 output hi-z/ input disabled output hi-z/ input enabled 19 p01 ppg2 retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 20 p02 ppg3/int5 input enabled input enabled input enabled 21 to 23 p03 to p05 tin0 to tin2 retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 24, 25 p06, p07 tot1, tot2 26 p10 sot0 27 p11 sin0 28 p12 sck0 29 p13 sot1 30 p14 sin1 31 p15 sck1 32 p16 ppg5/int6/ rx0* 3 input enabled input enabled input enabled
mb91265a series 37 (continued) *1 : init = l : indicates the pin status with init remaining at the ?l? level. *2 : init = h : indicates the pin status existing immediately after init transition from ?l? to ?h? level. *3 : c-can terminal is only loaded in MB91F267NA. pin no. pin name function at initializing at sleep mode at stop mode init = l* 1 init = h* 2 hi-z = 0 hi-z = 1 33 p17 ppg6/tx0* 3 output hi-z/ input disabled output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 34 p20 adtg1/ic2 35 p21 adtg2/ic3 36 p22 pwi0 37 p23 dtti 38 p24 cki 39 p25 ic0 40 p26 ic1 41 p27 general port 42 pg1 ppg0 49 p37 ppg4 50 p36 ppg7/int7 input enabled input enabled input enabled 52 to 57 p35 to p30 rto5 to rto0 retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 58 to 61 p40 to p43 int0 to int3 in put enabled input enabled input enabled
mb91265a series 38 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = av ss = 0 v. *2 : be careful not to exceed v cc + 0.3 v, for example, when the power is turned on. be careful not to let av cc exceed v cc , for example, when the power is turned on. *3 : the maximum output current is the peak value for a single pin. *4 : the average output current is the average curr ent for a single pin over a period of 100 ms. *5 : the total average output current is the aver age current for all pins over a period of 100 ms. *6 : avrhn = avrh1, avrh2 warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.5 v ss + 6.0 v analog power supply voltage* 1 av cc v ss ? 0.5 v ss + 6.0 v *2 analog reference voltage* 1 avrhn* 6 v ss ? 0.5 v ss + 6.0 v *2 input voltage* 1 v i v ss ? 0.3 v cc + 0.3 v analog pin input voltage* 1 v ia v ss ? 0.3 avcc + 0.3 v output voltage* 1 v o v ss ? 0.3 v cc + 0.3 v ?l? level maximum output current i ol ? 10 ma *3 ?l? level average output current i olav ? 8ma*4 ?l? level total maximum output current i ol ? 60 ma ?l? level total average output current i olav ? 30 ma *5 ?h? level maximum output current i oh ? ? 10 ma *3 ?h? level average output current i ohav ? ? 4ma*4 ?h? level total maximum output current i oh ? ? 30 ma ?h? level total average output current i ohav ? ? 12 ma *5 power consumption p d ? 600 mw operating temperature ta ? 40 + 105 c at single chip operating storage temperature tstg ? 55 + 125 c
mb91265a series 39 2. recommended operating conditions (vss = avss = 0 v) note : upon power up, it takes approx. 100 s for stabilization of internal power supply after the v cc power supply is stabilized. keep applying ?l? to init signal during that period. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 4.0 5.5 v at normal operating analog power supply voltage av cc v ss + 4.0 v ss + 5.5 v analog reference voltage avrh1 av ss av cc v for a/d converter 1 avrh2 av ss av cc v for a/d converter 2 operating temperature ta ? 40 + 105 c at single chip operating
mb91265a series 40 3. dc characteristics (v cc = 4.0 v to 5.5 v, v ss = av ss = 0 v) 4. flash memory write/erase characteristics * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter symbol pin conditions value unit remarks min typ max "h" level input voltage v ihs hysteresis input pin ? vcc 0.8 ? vcc + 0.3 v "l" level input voltage v ils hysteresis input pin ? vss ? 0.3 ? vss 0.2 v "h" level output voltage v oh other than p30 to p35 v cc = 5.0 v, i oh = 4.0 ma vcc ? 0.5 ?? v v oh2 p30 to p35 v cc = 5.0 v, i oh = 8.0 ma vcc ? 0.7 ?? v "l" level output voltage v ol other than p30 to p35 v cc = 5.0 v, i ol = 4.0 ma ?? 0.4 v v ol2 p30 to p35 v cc = 5.0 v, i ol = 12 ma ?? 0.6 v input leak current i li ? v cc = 5.0 v, v ss < v i < v cc ? 5 ? + 5 a pull-up resistance r pull init , pull-up pin ?? 50 ? k ? power supply current i cc v cc v cc = 5.0 v, 33 mhz ? 90 100 ma i ccs v cc v cc = 5.0 v, 33 mhz ? 60 80 ma at sleep i cch v cc v cc = 5.0 v, ta = + 25 c ? 300 ? aat stop input capacitance c in other than v cc , v ss , av cc , av ss , avrh1, avrh2 ?? 515pf parameter conditions value unit remarks min typ max sector erase time (4 kbytes sector) ta = + 25 c, vcc = 5.0 v ? 0.2 0.5 s not including time for internal writing before deletion. byte write time ta = + 25 c, vcc = 5.0 v ? 32 3600 s not including system-level overhead time. erase/write cycle ? 10000 ?? cycle flash memory data retention time average ta = + 85 c 20 ?? year *
mb91265a series 41 5. ac characteristics (1) clock timing ratings (v cc = 4.0 v to 5.5 v, v ss = av ss = 0 v) *1 : the values assume a gear cycle of 1/16. *2 : when the pll is used, the lower- limit frequency of the input clock to t he x0 and x1 pins determines depending on the pll multiplication. at 1 multiplication : more than 8 mhz at 2 to 8 multiplication : more than 4 mhz ? conditions for measuring the clock timing ratings parameter symbol pin conditions value unit remarks min typ max clock frequency f c x0 x1 ? 3.6* 2 ? 12 mhz for using the pll within the self-oscilla- tion enabled range, set the multiplier for the internal clock not to let the operating frequency exceed 33 mhz. clock cycle time t c x0 x1 83.3 ? 278* 2 ns input clock pulse width p wh p wl x0 ? 100 ?? ns the standard of the duty ratio is 40 % to 60 % . input clock rising, falling time t cf t cr x0 ??? 5 ns at external clock internal operating clock frequency f cp ? when 4.125 mhz is input as the x0 clock frequency and 8 multiplication is set for the pll of the oscillator circuit. 2.06* 1 ? 33 mhz cpu f cpp 2.06* 1 ? 33 mhz peripheral internal operating clock cycle time t cp ? 30.3 ? 485* 1 ns cpu t cpp 30.3 ? 485* 1 ns peripheral 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl c = 50 pf output pin
mb91265a series 42 ? operation assurance range ? internal clock setting range 0 (mhz) 5.5 4.0 f cp , f cpp 33 0.25 v cc (v) internal clock power supply voltage 33 (mhz) 16.5 4.125 8 : 8 4 : 4 1 : 1 notes : ? oscillation stabilization time of pll > 600 s ? the internal clock gear setting should be with in the value shown in clock timing ratings table. oscillation input clock f c = 4 . 192 mhz cpu : divided ratio for peripherals. internal clock peripheral (clkp) : cpu (clkb) : (pll multiplied by 8)
mb91265a series 43 (2) reset input ratings (v cc = 4.0 v to 5.5 v, v ss = av ss = 0 v) * : after the power is stable, l level is kept inputting to init for the duration of approximately 100 s until the internal power is stabilized. parameter sym- bol pin condi- tions value unit remarks min max init input time (at power-on and stop mode) t intl init ? oscillation time of oscillator + t c 10 ? ns * init input time (other than the above) t c 10 ? ns init 0.2 v cc t intl
mb91265a series 44 (3) uart timing (v cc = 4.0 v to 5.5 v, v ss = av ss = 0 v) notes : ? the above ratings are the valu es for clock synchronous mode. ? t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit min max serial clock cycle time t scyc sck0, sck1 internal shift clock mode 8 t cycp ? ns sck sot delay time t slov sck0, sck1, sot0, sot1 ? 80 + 80 ns valid sin sck t ivsh sck0, sck1, sin0, sin1 100 ? ns sck valid sin hold time t shix sck0, sck1, sin0, sin1 60 ? ns serial clock ?h? pulse width t shsl sck0, sck1 external shift clock mode 4 t cycp ? ns serial clock ?l? pulse width t slsh sck0, sck1 4 t cycp ? ns sck sot delay time t slov sck0, sck1, sot0, sot1 ? 150 ns valid sin sck t ivsh sck0, sck1, sin0, sin1 60 ? ns sck valid sin hold time t shix sck0, sck1, sin0, sin1 60 ? ns
mb91265a series 45 ? internal shift clock mode ? external shift clock mode sck0, sck1 t scyc t slov t ivsh t shix v ol v ol v oh v oh v ol v oh v ol v oh v ol sot0, sot1 sin0, sin1 t slsh t slov t ivsh t shix t shsl v oh v ol v oh v ol v oh v ol v oh v ol v ol v ol sck0, sck1 sot0, sot1 sin0, sin1
mb91265a series 46 (4) free-run timer clock, pwc inpu t, and reload timer trigger timing (v cc = 4.0 v to 5.5 v, v ss = av ss = 0 v) note : t cycp indicates the peripheral clock cycle time. (5) trigger input timing (v cc = 4.0 v to 5.5 v, v ss = av ss = 0 v) note : t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit min max input pulse width t tiwh t tiwl cki, pwi0, tin0 to tin2 ? 4 t cycp ? ns parameter symbol pin conditions value unit min max input capture trigger input t ic ic0 to ic3 ? 5 t cycp ? ns a/d activation trigger input t adtg adtg1, adtg2 ? 5 t cycp ? ns t tiwh t tiwl v oh v oh v ol v ol cki, pwi0, tin0 to tin2 ic0 to ic3 adtg1, adtg2 t adtg , t ic v ol v ol
mb91265a series 47 6. electrical characteristics for the a/d converter (v cc = avcc = 5.0 v, v ss = av ss = 0 v) *1 : measured in the cpu sleep state *2 : vcc = avcc = 5.0 v, machine clock at 33 mhz *3 : the current when the cpu is in stop m ode and the a/d converter is not operating (at vcc = avcc = avrhn = 5.0 v) *4: avrhn = avrh1, avrh2 note : the above does not guar antee the inter-unit accuracy. set the output impedance of the external circuit 2 k ? . parameter sym- bol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error* 1 ?? ? 4 ? + 4lsb at avrhn* 4 = 5.0 v linearity error* 1 ?? ? 3.5 ? + 3.5 lsb differential linearity error* 1 ?? ? 3 ? + 3lsb zero transition voltage* 1 v ot an0 to an10 avss ? 3.5lsb avss + 0.5lsb avss + 4.5lsb v full transition voltage* 1 v fst an0 to an10 avrh ? 5.5lsb avrh ? 1.5lsb avrh + 2.5lsb v conversion time ?? 1.2* 2 ?? s analog port input current i ain an0 to an10 ?? 10 a analog input voltage v ain an0 to an10 avss ? avrh v reference voltage ? avrhn* 4 avss ? avcc v analog power supply current (analog + digital) i a avcc ? 2 ? ma per 1 unit i ah * 3 ?? 100 a per 1 unit reference power supply current (between avrh and av ss ) i r avrhn* 4 ? 1 ? ma per 1 unit avrhn* 4 = 5.0 v, at av ss = 0 v i rh * 3 ?? 100 a per 1 unit at stop analog input capacitance ?? ? 10 ? pf inter-channel disparity ? an0 to an10 ?? 4lsb
mb91265a series 48 definition of a/d converter terms resolution : analog variation that is recognized by an a/d converter. linearity error : zero transition point (00 0000 0000 00 0000 0001) and full-scale transition point. difference between the li ne connected (11 1111 1110 11 1111 1111) and actual conversion character- istics. differential linearity error : deviation of input voltage, that is required for changing output code by 1 lsb, from an ideal value. total error : this error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh 0.5 lsb' {1 lsb' (n ? 1) + 0.5 lsb'} 1.5 lsb' digital output analog input total error ideal characteristics actual conversion characteristics v nt (measurement value) actual conversion characteristics n : a/d converter digital output value v nt : a voltage at which digital output transits from (n + 1) to n. v ot ? (ideal value) = av ss + 0.5lsb? [v] v fst ? (ideal value) = avrh ? 1.5 lsb? [v] 1lsb? (ideal value) = avrh ? av ss [v] total error of digital output n = v nt ? {1 lsb? (n ? 1) + 0.5 lsb?} 1024 1 lsb?
mb91265a series 49 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh {1 lsb (n ? 1) + v ot } n ? 1 h av ss avrh n ? 2 h n h n + 1 h digital output analog input linearity error ideal characteristics actual conversion characteristics v fst (measurement value) actual conversion characteris tics v ot ( measurement value) digital output analog input differential linearity error actual conversion characteristics ideal characteristics v fst (measurement value) v nt (measurement value) v nt (measurement value) actual conversion characteristics n : a/d converter digital output value v ot : a voltage at which digital output transits from 000 h to 001 h . v fst : a voltage at which digital output transits from 3fe h to 3ff h . linearity error in digital output n = v nt ? { 1 lsb (n ? 1) + v ot } [lsb] 1 lsb differential linearity error in digital output n = v ( n + 1 ) t ? v nt ? 1 [lsb] 1 lsb 1 lsb = v fst ? v ot [v] 1022
mb91265a series 50 example characteristics (continued) 6 5 4 3 2 1 0 4.0 4.5 5.0 5.5 v cc (v) v oh (v) 400 350 300 250 200 150 100 50 0 4.0 4.5 5.0 5.5 v cc (v) v ol (mv) 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 v cc (v) r (k ? ) 100 90 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 v cc (v) i cc (ma) 15 20 25 30 35 i cc (ma) 4.0 v 4.5 v 5.0 v 5.5 v 0 10 20 30 40 50 60 70 80 90 100 ?h? level output voltage vs. power supply voltage ?l? level output voltage vs. power supply voltage pull-up resistor vs. power supply voltage power supply current vs. power supply voltage power supply current vs. internal operating clock frequency (mb91266a) internal operating clock frequency [mhz] power supply voltage
mb91265a series 51 (continued) 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 v cc (v) i ccs (ma) 100 90 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 v cc (v) i cch ( a) 5.5 2 1.5 1 0.5 0 4.0 4.5 5.0 v cc (v) i a (ma) 5.5 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 v cc (v) i r (ma) 5.5 power supply current (at stop) vs. power supply voltage a/d conversion block per 1 unit (33 mhz) analog power supply current vs. power supply voltage a/d conversion block per 1 unit (33 mhz) reference power supply current vs. power supply voltage power supply current (at sleep) vs. power supply voltage
mb91265a series 52 ordering information part number package remarks mb91266apmc-g-xxx 64-pin plastic lqfp (fpt-64p-m23) mb91266apmc-gs-xxx mb91266apmc-g-xxxe1 lead-free package mb91266apmc-gs-xxxe1 lead-free package mb91f267apmc-g mb91f267apmc-gs mb91f267apmc-ge1 lead-free package mb91f267apmc-gse1 lead-free package MB91F267NApmc-g package loaded c-can MB91F267NApmc-gs package loaded c-can MB91F267NApmc-ge1 lead-free package, package loaded c-can MB91F267NApmc-gse1 lead-free package, package loaded c-can mb91v265acr-es 401-pin ceramic pga (pga-401c-a02)
mb91265a series 53 package dimension please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lfqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m2 3 ) (fpt-64p-m2 3 ) c 200 3 fujit s u limited f640 3 4 s -c-1-1 0.65(.026) 0.10(.004) 1 16 17 3 2 49 64 33 4 8 * 12.00 0.10(.472 .004) s q 14.00 0.20(.551 .00 8 ) s q index 0. 3 2 0.05 (.01 3 .002) m 0.1 3 (.005) 0.145 0.055 (.0057 .0022) "a" .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.50 0.20 (.020 .00 8 ) 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb91265a series 54 main changes in this edition the vertical lines marked in the left side of the p age show the changes. page section change results ?? changed the name of the series as follows: mb91265 series mb91265a series ?? added the following part numbers: mb91v265a : evaluation product 8 pin description changed the description of the function of the x0 pin as follows: clock (oscillation) output terminal. clock (oscillation) input terminal. changed the description of the function of the x1 pin as follows: clock (oscillation) input terminal. clock (oscillation) output terminal. 14 handling devices removed the x0a pin and the x1a pi n from the description of the crystal oscillator circuit. 47 electrical characteristics 6. electrical characteristics for the a/d converter changed the units of the zero transition voltage and the full transition voltage as follows: lsb v 52 ordering information added the following part numbers: mb91v265acr-es
mb91265a series f0701 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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